1. Field of the Invention
The invention relates to a non-volatile memory, and more particularly to a floating gate transistor type non-volatile memory having a function of an orthogonal memory or a content address memory.
2. Description of the Related Art
In a floating gate transistor type non-volatile memory such as UVEPROM (Ultra Violet Erasable Programmable Read Only Memory) and a flash type EEPROM (Electrically Erasable Programmable Read Only Memory), it is possible to electrically write data into the memory. In particular, it is possible to electrically erase data in a flash type EEPROM.
Each of memory cell employed in such memories is constituted by a cell transistor having a source, a drain, a control gate, and a floating gate. The cell transistor thus constructed stores data therein utilizing the fact that a threshold voltage is varied in accordance with a quantity of charges accumulated in the floating gate. On reading data stored in the memory cell, the content of stored data is judged in dependence on whether a current flows between the drain and the source of the cell transistor when a reading voltage is applied to the control gate thereof. In writing and erasing the data, on the other hand, a higher voltage than the reading voltage is applied to make electric charges to move between the floating gate and a substrate in which the cell transistor is formed, thereby controlling a quantity of charges to be accumulated in the floating gate.
FIG. 1 is a conceptual block diagram of a conventional non-volatile memory constituted as a flash type EEPROM.
The illustrated non-volatile memory comprises a memory cell array 1. This memory cell array 1 includes a plurality of memory cell transistors 2 arranged in a matrix. Each of the memory cell transistors 2 has a floating gate. The cell array 1 further has a plurality of gate lines GL associated with each of rows of the memory cells 2, and each of the gate lines GL is in electrical connection with control gates of the cell transistors 2 disposed in an associated row. There are also disposed a plurality of drain lines DL associated with each of columns of the cell transistors 2, and each of the drain lines DL is in electrical connection with drains of the cell transistors 2 disposed in an associated column. A plurality of source lines SL are in electrical connection with sources of the transistors of each of the memory cells arranged in a matrix.
The non-volatile memory further includes a column address buffer circuit 3, a row address buffer circuit 4, a row decoder 5, a source voltage switching circuit 6, a column decoder 7, a writing/reading circuit 8, and a voltage switching circuit 9. The column address buffer circuit 3 and the row address buffer circuit 4 receive column address signals ADc and row address signals ADr, respectively, from external devices (not illustrated), and accumulate them therein and transmitting them. The row decoder 5 applies a ground potential to all of the gate lines GL of the cell array 1 on an erasing operation in which erasing signals EE are in active level. On operations other than an erasing operation, such as writing and reading operations, the row decoder 5 selects one of the gate lines GL in accordance with the row address signals ADr transmitted form the row address buffer circuit 4, and further applies a selection voltage to the selected gate line. The selection voltage is in general 12 V in a writing operation, and 5 V in a reading operation. The source voltage switching circuit 6 applies a voltage for erasion, which is in general 12 V, to the source lines SL on an erasing operation, and applies a ground voltage to the source lines SL in operations other than an erasing operation. The column decoder 7 selects one of the drain lines DL in accordance with the column address signals ADc transmitted from the column address buffer circuit 3. The writing/reading circuit 8 applies a voltage for writing, which is in general 6 V and which corresponds to data Di received therein, on a writing operation, and applies a bias voltage, which is in general 1 V, to the selected drain line DL on a reading operation. The writing/reading circuit 8 further detects a voltage level responsive to a current flowing through the selected drain line DL and amplifies the detected voltage level, and generates an output Do. The voltage switching circuit 9 generates a voltage on a writing and a reading operations. The voltage is supplied to the drain lines DL and the gate lines GL through the writing/reading circuit 8 and the column decoder 7, and the row decoder 5, respectively.
Reading of data stored in the memory cell 2 is carried out as follows. First, the source lines SL are grounded. Then, the row decoder 5 applies a supply voltage to a selected gate line, and applies a ground voltage to non-selected gate lines. The column decoder 7 selects one of the drain lines DL, and then the writing/reading circuit 8 detects a current running through the thus selected drain line DL, thereby reading data stored in the memory cell being performed. In general, the logic 1 is assigned when the current is detected, whereas the logic 0 is assigned when the current is not detected.
Writing data to the memory cell 2 is carried out as follows. The row decoder 5 selects one of gate lines GL, and applies approximately 12 V to the selected gate line GL. The writing/reading circuit 8 applies approximately 6 V to the drain lines DL. Thus, hot electrons are injected in a floating gate of the cell transistors 2. Thus, data writing operation is completed. A threshold voltage of the memory cell transistors, which is about 7 V, becomes higher than a gate voltage to be generated on reading operation.
An erasing operation is carried out by applying a ground voltage to all of the gate lines GL and also applying a high voltage, which is in general about 12 V, to the source lines SL to thereby extract electrons to a source out of floating gates of all the memory cell transistors of the cell array 1 by virtue of tunnel effect. A threshold voltage of the memory cell transistors lowers below a gate voltage to be generated on a reading operation.
The flash type memory thus constructed is often employed in an image processor in which two-dimensional data are arranged in a matrix, such as an image bit map and letter font, and data successively situated in a row direction is considered as a unit. A plurality of such units arranged in a column direction are stored in the image processor. When lateral turning of an image bit map or letter font is to be carried out, data stored in the image processor with data successively situated in a row direction being considered as a unit is read out as if such data successively situated in a column direction is a unit. A memory having a function by which the above mentioned operation can be carried out at high speed is referred to as an orthogonal memory.
FIGS. 2A and 2B illustrate block diagrams of a conventional volatile memory having a function of an orthogonal memory.
The illustrated volatile memory comprises a cell array 11. This cell array 11 includes a plurality of memory cells 12 arranged in a matrix. Each of the memory cells 12 has transistors Q1 to Q8, as illustrated in FIG. 2B. There are disposed a plurality of first word lines WL1j (j indicates an integer raging from 1 to m both inclusive) associated with each of rows of the memory cells 12, and each of the first word lines WL1j is in electrical connection with first selection terminals of the memory cells 12 disposed in an associated row. Herein, the first selection terminals indicate gates of the transistors Q5 and Q6. There are also disposed a plurality of first bit lines BL1ia and BL1ib (i indicates an integer ranging from 1 to n both inclusive) associated with each of columns of the memory cells 12, and each of the first bit lines BL1ia and BL1ib is in electrical connection with first data terminals of the memory cells 12 disposed in an associated column. Herein, the first data terminals indicate drains of the transistors Q5 and Q6. There are further disposed a plurality of second word lines WL2i associated with each of columns of the memory cells 12, and each of the second word lines WL2i is in electrical connection with second selection terminals of the memory cells 12 disposed in an associated column. Herein, the second selection terminals indicate gates of the transistors Q7 and Q8. There are further disposed a plurality of second bit lines BL2ja and BL2jb associated with each of rows of the memory cells 12, and each of the second bit lines BL2ja and BL2jb is in electrical connection with second data terminals of the memory cells 12 disposed in an associated row. Herein, the second data terminals indicate drains of the transistors Q7 and Q8.
The volatile memory further includes a column address buffer circuit 13, a row address buffer circuit 14, a row decoder 15, a column decoder 17, a row writing/reading circuit 18, and a column writing/reading circuit 19. The column address buffer circuit 13 and the row address buffer circuit 14 receive column address signals ADc and row address signals ADr, respectively, from peripheral devices (not illustrated), and accumulate them therein and transmitting them. The row decoder 15 selects one of the first word lines WL1j in accordance with the row address signals ADr transmitted form the row address buffer circuit 14. The column decoder 17 selects one of the second word lines WL2i in accordance with the column address signals ADc transmitted from the column address buffer circuit 13. On a row reading operation in which row reading signals are in active level, the row writing/reading circuit 18 detects data stored in the memory cells 12 connected to the first word line WL1j selected by the row decoder 15, in accordance with the signals appearing through the first bit lines BL1ia and BL1ib, and amplifies the thus detected data, and transmits the amplified data as an output Do1. On a row writing operation in which row writing signals are in active level, the row writing/reading circuit 18 provides row writing signals corresponding to input data Di1 with the first bit lines BL1ia and BL1ib. The column writing/reading circuit 19 detects data stored in the memory cells 12 connected to the second word line WL2i selected by the column decoder 17, in accordance with the signals appearing through the second bit lines BL2ja and BL2jb, and amplifies the thus detected data, and transmits the amplified data as an output Do2. On a column writing operation in which column writing signals are in active level, the column writing/reading circuit 19 provides column writing signals corresponding to input data Di2 with the second bit lines BL2ja and BL2jb.
In this orthogonal memory, reading or writing data in a row direction can be carried out by means of the row decoder 15 and the row writing/reading circuit 18. Similarly, reading or writing data in a column direction can be carried out by means of the column decoder 17 and the column writing/reading circuit 19.
There has been suggested another sample of an orthogonal memory by Akio Kokubu, Minoru Kuroda and Tatsumi Furuya: Orthogonal Memory--A Step Toward Realization of Large Capacity Associative Memory, IFIP, pp 165-174, 1986. FIG. 3 illustrates the memory cell, which consists of a flip-flop circuit having four transfer gates. Compared with a conventional static RAM, two transfer gates Q6 and Q8 are added for bit slice access to drive the word lines. They are paired with transfer gates Q5 and Q7, and are connected to the flip-flop circuit. The gate of Q7 is connected to the word line (0) paired with the word line (1). This makes orthogonal control possible.
In bit slice access, bit lines (0) and (1) are activated to high, and the transfer gates Q6 and Q8 are turned on. When the cell state is held as A being high and B being low, the word line (1) is activated to high via the transfer gate Q6. The transfer gate Q5 is also turned on by activation of the word line (1). The cell state, nevertheless, is not affected because A is already high. The word line (0) is not activated to high via the transfer gate Q8 because B is low. Thus, the transfer gate Q7 is not turned on and the cell state is not affected.
In word slice access, word lines (0) and (1) are activated to high, and the transfer gates Q5 and Q7 are turned on. Operation of the memory proceeds in the same way as bit slice access.
As aforementioned, the orthogonal memory can carry out operations of reading and writing data arranged in a matrix at high speed in both row and column directions, and hence is quite useful for various operations such as lateral turning of an image bit map or letter font.
As another type of a memory suitable for use of a device such as a data base processor is there a content address memory. The content address memory has a function for carrying out collective comparison of a plurality of words stored therein with a given word to be retrieved. The content address memory is applicable to a translation lookaside buffer (TLB) of a cash memory capable of carrying out high speed comparison of given data with stored data, and also applicable to an apparatus for retrieving data base.
FIG. 4A is a block diagram of a conventional volatile memory having a function of a content address memory. FIG. 4B is an enlarged view illustrating a memory cell. The illustrated volatile memory comprises a cell array 21. The cell array 21 includes a plurality of memory cells 22 arranged in a matrix. Each of the memory cells 22 has transistors Q1 to Q10, as illustrated in FIG. 4B. There are disposed a plurality of word lines WL1j associated with each of rows of the memory cells 22, and each of the word lines WL1j is in electrical connection with selection terminals of the memory cells 22 disposed in an associated row. Herein, the selection terminals indicate gates of the transistors Q5 and Q6. There are also disposed a plurality of bit lines BL1ia and BL1ib associated with each of columns of the memory cells 22, and each of the bit lines BL1ia and BL1ib is in electrical connection with data terminals of the memory cells 22 disposed in an associated column. Herein, the data terminals indicate drains of the transistors Q5 and Q6. There are further disposed a plurality of retrieval lines ILia and ILib associated with each of columns of the memory cells 22, and each of the retrieval lines ILia and ILib is in electrical connection with selection terminals of the memory cells 22 disposed in an associated column. Herein, the selection terminals indicate gates of the transistors Q9 and Q10. There are further disposed a plurality of coincidence lines MLj associated with each of rows of the memory cells 22, and each of the coincidence lines MLj is in electrical connection with coincidence terminals of the memory cells 22 disposed in an associated row. Herein, the coincidence terminals indicate drains of the transistors Q7 and Q8.
The volatile memory further includes a row address buffer circuit 23, a row decoder 24, a writing/reading circuit 25, a retrieval data register 26 and a coincidence judging circuit 27. The row address buffer circuit 23 receive address signals AD from peripheral devices (not illustrated), and accumulate them therein and transmitting them. The row decoder 24 selects one of the word lines WL1j in accordance with the address signals AD transmitted form the row address buffer circuit 23. On a reading operation in which reading signals are in active level, the writing/reading circuit 25 detects data stored in the memory cells 22 connected to the word line WL1j selected by the row decoder 24, in accordance with the signals appearing through the bit lines BL1ia and BL1ib, and amplifies the thus detected data, and transmits the amplified data as an output Do. The writing/reading circuit 25, on a writing operation in which writing signals are in active level, provides the writing signals corresponding to input data Di with the bit lines BL1ia and BL1ib. The retrieval data register 26 accumulates retrieval data SD transmitted from outside, and on a retrieving operation in which retrieval signals are in active level, the retrieval data register 26 provides retrieval signals corresponding to the retrieval data SD with the retrieval lines ILia and ILib. The coincidence judging circuit 27, on a retrieving operation, judges as to whether data stored in the memory cells 22 connected to each of the coincidence lines ML is coincident with the retrieval data SD, in accordance with signals transmitted through the coincidence lines MLj. The coincidence judging circuit 27 amplifies a result, and provides as an output MD.
In this volatile memory, data stored in the memory cells connected to one of the word lines WL1j is treated as one word. The row decoder 24 and the writing/reading circuit 25 cooperate to make it possible to read and write data word by word. In addition, the retrieval data register 26 and the coincidence judging circuit 27 cooperate to make it possible to retrieve all words in parallel as to whether a given word is coincident with the retrieval data SD.
However, since these memories are volatile, data stored in the memories is erased by turning a power supply off. Hence, complicated operations are necessary on turning off a power supply, such as moving the stored data to a non-volatile device such as a hard disk and writing them again into the volatile memories when a power supply is turned on again. Even if those volatile memories can be modified into non-volatile memories by using floating gate transistors, for instance, as the transistors Q1 and Q2 of the memory cell, it would be necessary to use eight orthogonal memories or ten content address memories for one memory cell, making it quite difficult to obtain a smaller size, a larger capacitance and lower consumption of electrical power.
On the other hand, in the earlier mentioned floating gate transistor type non-volatile memory, since one memory cell is composed of one floating gate transistor, it is possible to obtain a smaller size, a larger capacitance and lower consumption of electrical power. However, the structure of the non-volatile memory as it is cannot perform a function of an orthogonal memory and a content address memory in which four terminals are required for one memory cell, such as a selection terminal, a data terminal, a retrieval terminal and a coincidence terminal.
As having been described, a conventional floating gate transistor type non-volatile memory has an advantage that it is possible to obtain a smaller size, a larger capacitance and lower consumption of electrical power since one memory cell is composed of one floating gate transistor, but also has a disadvantage that it is not possible to perform a function of an orthogonal memory and a content address memory in which four terminals are required for one memory cell, such as a selection terminal, a data terminal, a retrieval terminal and a coincidence terminal. A conventional memory having a function of an orthogonal memory and a content address memory needs to carry out complicated operations such as moving stored data into another medium and writing them again, since the memory is volatile. Even if the volatile memory in question can be modified into a non-volatile memory by replacing floating gate transistors with originally used transistors of the memory cell, it would be necessary to use a number of transistors for one memory cell, making it quite difficult to obtain a smaller size of a memory, a larger capacitance and lower consumption of electrical power.